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CXR704060
CMOS 32-bit Single Chip Microcomputer
Description The CXR704060 is a CMOS 32-bit microcomputer integrating on a single chip a micro processor unit having a 32-bit RISC CPU as its core, and a signal processing block having an accelerator circuit suited for arithmetic signal processing. Adoption of this arithmetic signal processing accelerator circuit enables flexible support of various signal processing systems. The microcomputer block incorporates Memory Stick interface, a MagicGate, FLASH memory interface, USB interface, D/A converter for audio applications, A/D converter, serial interface, I2C bus interface, timer and PWM pulse generator as well as basic configurations like a 32-bit RISC CPU, ROM, RAM, and I/O ports. It also provides the idle/sleep/stop functions that enable lower power consumption. Features * CPU * Minimum instruction cycle * Incorporated ROM * Incorporated RAM * Peripheral hardware -- Bus interface unit -- DMA controller -- A/D converter -- Serial interface 208 pin TFLGA (Plastic)
SR11 series 32-bit RISC CPU core (ARM7TDMI) 44.29ns (fSRC: 22.5792MHz) 192K bytes 256K bytes 16-bit data bus, 24-bit address bus, 5 chip select outputs 4 channels 10-bit 8-analog input, successive approximation method Clock synchronization, 1 channel (Incorporated 128-byte buffer RAM) Clock synchronization, 1 channel (Incorporated 32-byte buffer RAM) Asynchronization, 2 channels 8 channels (timer output)
-- 8-bit timer -- Time-base timer -- Prescaler -- Watchdog timer 16 bits x 1 channel -- PWM pulse generator 8 bits x 1 channel -- 16-bit D/A converter for audio applications L channel, R channel -- Memory Stick interface 1 channel -- MagicGate -- Serial interface for EEPROM Serial interface for CXK2000, 1 channel -- USB interface Conforms to USB1.1, internal transceiver -- Flash memory interface 1-bit error correction function -- External interruption 10 channels (polarity selection and both edge detection possible) * Accelerator for arithmetic signal processing * Standby mode Idle/sleep/stop * Package 208-pin plastic TFLGA Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E02655-PS
AOUTR AOUTL MUTFGR MUTFGL FS256 ADDT DADT XBCK LRCK
SERIAL INTERFACE (CH1)
SERIAL INTERFACE (CH0)
I2C BUS INTERFACE
D/A CONVERTER
TRON TX TEX UDM UDP VBUS AVSPLL AVDPLL VDIOUS AVDUO USB INTERFACE KRB KCS KCLK KDO KDI EEPROM SERIAL INTERFACE MAGIC GATE CORE
MSINS MSDIO MSSCLK MSBS VDIOMS MEMORY STICK INTERFACE FWP FRE FWE FALE FCLE
DMAC (CH3) DMAC (CH2)
WATCHDOG TIMER FLASH MEMORY INTERFACE CLOCK GENERATOR/ SYSTEM CONTROLLER
FRB0 to FRB1
FCE0 to FCE1 FAD0 to FAD7 VDIODF LWR/LB UWR/UB WE RE WAIT
PRESCALLER/ TIME BASE TIMER
RAM 256K BYTES
BUS INTERFACE UNIT
EXTERNAL BUS
CS0, CS1, CS5 to CS7 D0 to D15 A0 to A23
ROM 192K BYTES
PORT R PORT Q PORT P PORT O PORT N PORT M PORT L
PORT K
PORT J
8
8
2
8
8
8
8
8
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Block Diagram
AVDDA AVSDA BEEP T3 SCS1 SI1 SO1 SCK1 TxD1 RxD1 SDA SCL EC0 TxD0 RxD0 PWM T1 EC2 UART (CH1) UART (CH0) 8-BIT TIMER (CH7) 8-BIT TIMER (CH6) 8-BIT TIMER (CH5) 8-BIT TIMER (CH4) 8-BIT TIMER (CH3) 8-BIT TIMER (CH1) 8-BIT TIMER/COUNTER (CH2)
INTERRUPT CONTROLLER
7
AN0 to AN7
VREFR VREFL 8-BIT TIMER/COUNTER (CH0) PWM PULSE GENERATOR RAM 8 2 2 RAM
DMAC (CH1) DMAC (CH0)
SCS0 SI0 SO0 SCK0 RAM
8
AVSAD
A/D CONVERTER
AVDAD
MSINS VBUS (USB SUSPEND) INT3 to INT9
DACK1 DREQ1 DACK0 DREQ0
XTAL EXTAL RST AVSOSC AVDMO
2 2 8 5 16 24
VIRTUAL MOBILE ENGINE
TDO TRST ARM7TDMI CPU CORE TCK TMS TDI
PORT I
PORT G PORT F
PORT E PORT D PORT C PORT B
PORT A
5
8
4
1
4
8
8
4
8
3
CXR704060
CXR704060
Pin Assignment (Top View) 208-pin TFLGA package
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V U T R P N M L K J H G F E D C B A 100 112 113 118 120 123 128 129 134 135 140 142 146 148 150 152
101 105 107 110 116 121 122 126 131 133 139 141 144 147 151 153 158 160
93 103 106
89 91
87 97
85 99
83 92
81 88
77 79
75 80
71 73
70 69
67 65
64 58
63 56
61 57 53
55 59 52 49 46 43 38 34 31 28 25 22 17 13 12 51 47 45 41 39 37 33 29 24 23 20 19 15 11 9 5
V U T R P N M L K J H G F E D C B A
104 108 114 117 124 127 132 137 143 149 154 157 156 159 161 163 162
102 100 115 119 125 130 136 138 145 155 165 164
98 111
95 96
94 90
86 84
82 78
76 74
72 68
66 62
60 50 48 42 36 32 26 18 14 8
54 44 40 35 30 27 21 16 10 6 4 207 3
173 171
177 175
180 179
187 185
191 189
193 194
195 197
199 205
1 203
7 2 206
166 167
169 168
174 170
178 172
183 176
182 181
184 186
192 188
196 190
200 198
202 201
208 204
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
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CXR704060
* Pin Assignment Table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin position E5 B2 C3 E4 B1 F4 C2 F5 C1 G4 D1 D2 E2 G5 E1 H4 F2 H5 F1 G1 J4 G2 H1 J1 H2 J5 K4 J2 K1 L4 K2 K5 L1 L2 M4 L5 Pin function VDIO0 PM4/A12 PM5/A13 PM6/A14 PM7/A15 PN0/A16 PN1/A17 PN2/A18 PN3/A19 PN4/A20 PN5/A21 PN6/A22 PN7/A23 DVSS7 FAD0 FAD1 FAD2 FAD3 FAD4 FAD5 FAD6 FAD7 FCLE FALE VDIODF FWE FRE FWP FCE0 FRB0 FCE1 FRB1 PP0 PP1 DVDD0 DVSS1 Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin position M1 M2 N1 N4 P1 M5 N2 P4 R1 P2 T1 N5 R2 P5 U1 T2 T3 R4 V2 U4 U3 U5 U2 R5 V3 P6 V4 V5 U6 R6 V6 P7 U7 V7 V8 R7 Pin function VDIO1 PO0/D0 PO1/D1 PO2/D2 PO3/D3 PO4/D4 PO5/D5 PO6/D6 PO7/D7 PB0/D8 PB1/D9 PB2/D10 PB3/D11 PB4/D12 PB5/D13 PB6/D14 PB7/D15 PA0/PWM PA1/SDA PA2/SCL PC0/SCK0 PC1/SO0 PC2/SI0 PC3/SCS0 DVSS2 VDIO2 KDI KRB KCLK KCS KDO TEST4 PE0/TxD0 PE1/RxD0 PE2/TXD1 PE3/RXD1 -4- Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin position U8 P8 V9 R8 V10 P9 U10 U9 V11 R9 V12 P10 V13 R10 V14 U11 V15 P11 U15 U12 V16 R11 R12 P12 U14 R13 U13 P14 V17 R14 U16 R15 U17 T16 T17 P15 Pin function PE4/SCK1 PE5/SO1 PE6/SI1 PE7/SCS1 TEST5 DVDD1 DVSS3 VDIO3 PF0/EC0/INT3 PF1/T1 PF2/EC2/INT4 PF3/T3 PF4/BEEP PG0/DACK0 PG1/DREQ0/INT5 PG2/DACK1/INT6 PG3/DREQ1/INT7 TEST2 TEST3 TEST0 TEST1 TEST6 EVA AVSAD AVDAD AN0 AN1 AN2 AN3 AN4 AN5 AN6/INT8 AN7/INT9 RST RAMBK VDBK
CXR704060
Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142
Pin position U18 R17 P13 T18 R18 N15 N14 P17 M15 P18 M14 N18 N17 M17 M18 L15 L14 L17 K15 L18 K18 K14 K17 J15 J17 J18 H18 J14 H15 H14 H17 G18 G17 F18
Pin function TDI TMS TCK TRST TDO VDIOJT DVDD2 DVSS4 VDIO4 PD0/CONNECT PD1/XVDATA PD2/DPLS PD3/DMNS PD4/TXDPLS PD5/TXDMNS PD6/TXENL PD7/SUSPEND VBUS VDIOUS UDM UDP TRON AVSDA VREFR AOUTR AOUTL VREFL AVDDA XTAL EXTAL AVDMO AVSOSC TX TEX
Pin No. 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
Pin position G15 F17 G14 E18 E17 D18 F15 C18 D17 B18 C17 E15 F14 C16 D15 B17 B16 A17 A16 A15 B15 D14 E14 B14 A14 A13 B13 A12 D13 A11 E13 B12 D12 A10
Pin function AVDUO AVSPLL AVDPLL PQ0 PQ1 PQ2 PQ3 PQ4 PQ5 PQ6 PQ7 DVSS8 VDIO7 PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7 DVSS9 VDIOMS MSDIO MSBS MSSCLK MSINS PI7 PI0/DADT PI1/ADDT PI2/LRCK PI3/XBCK PI4/FS2S6 PI5/MUTFGL
Pin No. 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Pin position E12 B11 D11 E11 A9 B9 B10 B8 D10 A8 E10 A7 D9 A6 E9 B7 E8 D8 E7 B6 D7 A5 E6 B5 A4 B4 D5 A3 D6 A2 D4 B3
Pin function PI6/MUTFGR DVDD3 DVSS5 VDIO5 PJ0/WAIT PJ1/RE PJ2/LWR/LB PJ3/UWR/UB PJ4/WE PK0/CS0 PK1/CS1 PK2 PK3 PK4 PK5/CS5 PK6/CS6 PK7/CS7 DVSS6 VDIO6 PL0/A0 PL1/A1 PL2/A2 PL3/A3 PL4/A4 PL5/A5 PL6/A6 PL7/A7 PM0/A8 PM1/A9 PM2/A10 PM3/A11 DVSS0
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CXR704060
Pin Functions Symbol PJ0/WAIT PJ1/RE PJ2/LWR/ LB I/O I/O / Input I/O / Output I/O / Output / Output (Port J) 5-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (5 pins) Function Wait input for external bus. Read signal output for external bus. Write strobe signal output for D0 to D7. Strobe signal output indicates access to D0 to D7. I/O power supply
PJ3/UWR/ UB PJ4/WE PK0/CS0, PK1/CS1 PK2 to PK4 PK5/CS5 to PK7/CS7
I/O / Output / Output I/O / Output I/O / Output I/O I/O / Output
Strobe signal Write strobe signal output output indicates for D8 to D15. access to D8 to D15. Write signal output for external bus.
(Port K) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port L) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port M) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port N) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins)
Chip select output for external bus. (2 pins)
Chip select output for external bus. (3 pins)
VDIO0 VDIO5 VDIO6
PL0/A0 to PL7/A7
I/O / Output
PM0/A8 to PM7/A15
I/O / Output
Address bus output for external bus. (24 pins)
PN0/A16 to PN7/A23
I/O / Output
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CXR704060
Symbol FAD0 to FAD7 I/O FCLE FALE FWE FRE FWP FCE0, FCE1 FRB0, FRB1
I/O Output Output Output Output Output Output Input
Function Flash memory interface data I/O. CLE output of flash memory interface. ALE output of flash memory interface. WE output of flash memory interface. RE output of flash memory interface. WP output of flash memory interface. CE output of flash memory interface. RB input of flash memory interface. (Port P) 2-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (2 pins) (Port O) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port B) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port A) 3-bit I/O port. I/O can be specified in 1-bit units. For Bit 0, pull-up resistor can be incorporated through program. (3 pins) (Port C) 4-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (4 pins)
I/O power supply
VDIODF
PP0, PP1
I/O
PO0/D0 to PO7/D7
I/O / I/O
Data bus I/O for external bus. (16 pins)
PB0/D8 to PB7/D15
I/O / I/O
VDIO1 VDIO2 VDIO3 8-bit PWM output. I2C bus interface data I/O. I2C bus interface clock I/O. Serial clock (CH0) I/O. Serial data (CH0) output. Serial data (CH0) input. Serial chip select (CH0) input.
PA0/PWM PA1/SDA PA2/SCL PC0/SCK0 PC1/SO0 PC2/SI0 PC3/SCS0 KDI KRB
I/O / Output I/O / I/O I/O / I/O I/O / I/O I/O / Output I/O / Input I/O / Input Input Input
Serial interface data input for EEPROM. Serial interface Ready/Busy input for EEPROM. -7-
CXR704060
Symbol KCLK KCS KDO PE0/TxD0 PE1/RxD0 PE2/TxD1 PE3/RxD1 PE4/SCK1 PE5/SO1 PE6/SI1 PE7/SCS1 PF0/EC0/ INT3 PF1/T1 PF2/EC2/ INT4 PF3/T3 PF4/BEEP PG0/DACK0 PG1/DREQ0/ INT5
I/O Output Output Output I/O / Output I/O / Input I/O / Output I/O / Input I/O / I/O I/O / Output I/O / Input I/O / Input I/O / Input / Input I/O / Output I/O / Input / Input I/O / Output Output / Output I/O / Output I/O / Input / Input (Port G) 4-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (4 pins) (Port E) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins)
Function Serial interface clock output for EEPROM. Serial interface chip select output for EEPROM. Serial interface data output for EEPROM. UART (CH0) transmit data output. UART (CH0) receive data input. UART (CH1) transmit data output. UART (CH1) receive data input. Serial clock (CH1) I/O. Serial data (CH1) output. Serial data (CH1) input. Serial chip select (CH1) input. (Port F) Lower 4 bits are for I/O; upper 1 bit is output-only 5-bit port. For lower 4 bits, I/O can be specified in 1-bit units. For lower 4 bits, pull-up resistor can be incorporated through program in 1-bit. (5 pins) External event input to 8-bit timer (CH0). External event input to 8-bit timer (CH2). External interruption request input. External interruption request input.
I/O power supply
8-bit timer (CH1) output.
VDIO1 VDIO2 VDIO3
8-bit timer (CH3) output. Beep output. Transfer request acknowledge signal output from DMA controller (CH0). Transfer request External input to DMA interruption controller (CH0). request input. Transfer request acknowledge External signal output interruption from DMA request input. controller (CH1). Transfer request External input to DMA interruption controller (CH1). request input.
PG2/DACK1/ INT6
I/O / Output / Input
PG3/DREQ1/ INT7 AN0 to AN5 AN6/INT8, AN7/INT9
I/O / Input / Input Input Input / Input
Analog input to A/D converter. (6 pins) Analog input to A/D converter. (2 pins) External interruption request input. (2 pins) AVDAD
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CXR704060
Symbol PD0/ CONNECT PD1/XVDATA PD2/DPLS PD3/DMNS PD4/TXDPLS
I/O I/O / Input I/O / Input I/O / Input I/O / Input I/O / Output (Port D) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins)
Function USB connection input. (for external USB transceiver) USB receive data input. (for external USB transceiver) USB D+ data input. (for external USB transceiver) USB D- data input. (for external USB transceiver) USB D+ data output. (for external USB transceiver) USB D- data output. (for external USB transceiver) USB data control output. (for external USB transceiver) USB suspend output. (for external USB transceiver) USB power signal input. (USB connection detection signal input, for internal USB transceiver) USB D- data I/O. (for internal USB transceiver) USB D+ data I/O. (for internal USB transceiver) UDP pull-up resistor connection control output. Internal DAC reference voltage output. (Lch) Internal DAC Lch output. Internal DAC Rch output. Internal DAC reference voltage output. (Rch) (Port Q) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port R) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins)
I/O power supply
VDIO4
PD5/TXDMNS I/O / Output PD6/TXENL PD7/ SUSPEND VBUS UDM UDP TRON VREFL AOUTL AOUTR VREFR I/O / Output I/O / Output Input I/O I/O Output Output Output Output Output
VDIOUS
AVDDA
PQ0 to PQ7
I/O
VDIO7
PR0 to PR7
I/O
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CXR704060
Symbol PI0/DADT PI1/ADDT PI2/LRCK PI3/XBCK PI4/FS256 PI5/MUTFGL PI6/MUTFGR PI7 MSDIO MSBS MSSCLK MSINS TEST4
I/O I/O / Output I/O / Input I/O / I/O I/O / I/O I/O / Output I/O / Output I/O / Output I/O I/O Output Output Input Input (Port I) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins)
Function Audio data output to external DAC. (for test output) Audio data input from external ADC. (for test input) L/R sampling clock I/O to external DAC/ADC. (44.1kHz) Bit clock I/O to external DAC/ADC. (2.822MHz) 256fs clock output. (11.2896MHz) Zero data detection signal output. (Lch) Zero data detection signal output. (Rch)
I/O power supply
VDIO0 VDIO5 VDIO6
Memory Stick interface data I/O. Memory Stick interface bus state output. Memory Stick interface clock output. Memory Stick interface card detection input. (INT0) Test input. Test input. Test input. Test output. EVA mode switching input. Data input for JTAG boundary scanning test. Test mode control input for JTAG boundary scanning test. Clock input for JTAG boundary scanning test. Reset input for JTAG boundary scanning test. Data output for JTAG boundary scanning test. Oscillation connector for main oscillation. (When a clock is supplied externally, input it to EXTAL; opposite phase clock should be input to XTAL.) Test output. Oscillation connector for sub oscillation. (When a clock is supplied externally, input it to TEX; opposite phase clock should be input to TX.) System reset input. Control signal input for RAM backup. AVDMO VDIO1 VDIO2 VDIO3 AVDUO VDIOJT VDIO1 VDIO2 VDIO3 VDIOMS
TEST2, TEST3 Input TEST0, TEST1 Input TEST6 EVA TDI TMS TCK TRST TDO EXTAL XTAL TEST5 TEX TX RST RAMBK Output Input Input Input Input Input Output Input Output Output Input Output Input Input
AVDAD
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CXR704060
Symbol VDBK AVDAD AVSAD AVDDA AVSDA AVDPLL AVSPLL AVDMO AVDUO AVSOSC VDIODF VDIOMS VDIOJT VDIOUS VDIO0 to VDIO7 DVDD0 to DVDD3 DVSS0 to DVSS9
I/O
Function Positive power supply for RAM backup. Positive power supply for A/D converter. GND for A/D converter. Positive power supply for internal DAC.1 GND for internal DAC. Positive power supply for PLL.2 GND for PLL. Positive power supply for main clock oscillator.1 Positive power supply for sub clock oscillator.2 Main clock and sub clock oscillator GND. Positive power supply for flash memory interface. Positive power supply for Memory Stick interface. Positive power supply for JTAG. Positive power supply for USB transceiver. I/O interface positive power supply. Positive power supply. (Connect all four VDD pins to positive power supply.) GND. (Connect all ten DVss pins to GND.)
I/O power supply
1 AVDDA and AVDMO must be the same potential. 2 AVDPLL and AVDUO must be the same potential.
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CXR704060
* I/O Power Supply and Pin Correspondence Table I/O power supply VDIO0 VDIO5 VDIO6 VDIODF Digital/Analog Symbol PI0/DADT, PI1/ADDT, PI2/LRCK, PI3/XBCK, PI4/FS256, PI5/MUTFGL, PI6/MUTFGR, PJ0/WAIT, PJ1/RE, PJ2/LWR/LB, PJ3/UWR/UB, PJ4/WE, PK0/CS0, PK1/CS1, PK2, PK3, PK4, PK5/CS5, PK6/CS6, PK7/CS7, PL0/A0 to PL7/A7, PM0/A8 to PM7/A15, PN0/A16 to PN7/A23 FAD0 to FAD7, FCLE, FALE, FWE, FRE, FWP, FCE0, FRB0, FCE1, FRB1 PP0, PP1, PO0/D0 to PO7/D7, PB0/D8 to PB7/D15, PA0/PWM, PA1/SDA, PA2/SCL, PC0/SCK0, PC1/SO0, PC2/SI0, PC3/SCS0, KDI, KRB, KCLK, KCS, KDO, TEST4, PE0/TxD0, PE1/RxD0, PE2/TxD1, PE3/RxD1, PE4/SCK1, PE5/SO1, PE6/SI1, PE7/SCS1, TEST5, PF0/EC0/INT3, PF1/T1, PF2/EC2/INT4, PF3/T3, PF4/BEEP, PG0/DACK0, PG1/DREQ0/INT5, PG2/DACK1/INT6, PG3/DREQ1/INT7, TEST0 to TEST3, TEST6, EVA AN0 to AN5, AN6/INT8, AN7/INT9 (RST, RAMBK) 1 TDI, TMS, TCK, TRST, TDO PD0/CONNECT, PD1/XVDATA, PD2/DPLS, PD3/DMNS, PD4/TXDPLS, PD5/TXDMNS, PD6/TXENL, PD7/SUSPEND, VBUS UDM, UDP, TRON VREFR, AOUTR, AOUTL, VREFL XTAL, EXTAL TX, TEX PQ0 to PQ7, PR0 to PR7 MSDIO, MSBS, MSSCLK, MSINS, PI7
Digital power supply
Digital power supply
VDIO1 VDIO2 VDIO3
Digital power supply
AVDAD VDIOJT VDIO4 VDIOUS AVDDA AVDMO AVDUO VDIO7 VDIOMS
Analog power supply Digital power supply Digital power supply Digital power supply Analog power supply Analog power supply Analog power supply Digital power supply Digital power supply
1 The H level input to RST and RAMBK must be the same potential as DVDD0 to DVDD3 and VDBK.
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CXR704060
I/O Circuit Format for Pins Pin
PWM MPX PA register PASL register "0" after a reset PAD register
Circuit format
VDIO
After a reset
PA0/PWM
"0" after a reset PAPUL register "0" after a reset Data bus RD MPX Input data latch
VDIO
Hi-Z
IP CMOS Schmitt input
SDA, SCL MPX PA register PASL register "0" after a reset
PA1/SDA PA2/SCL
PAD register "0" after a reset Data bus RD SDA, SCL MPX Input data latch IP CMOS Schmitt input
Hi-Z
VDIO D8 to D15 MPX PB register PBSL register "0" after a reset DE
PB0/D8 to PB7/D15
MPX PBD register "0" after a reset PBPUL register "0" after a reset Data bus RD D8 to D15 MPX Input data latch IP CMOS Schmitt input VDIO
Hi-Z
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CXR704060
Pin
Circuit format
VDIO SCK0 MPX PC register PCSL register "0" after a reset SCK0E MPX
After a reset
PC0/SCK0
PCD register "0" after a reset PCPUL register "0" after a reset Data bus RD SCK0 MPX Input data latch IP CMOS Schmitt input VDIO
Hi-Z
VDIO SO0 MPX PC register PCSL register "0" after a reset SO0E MPX
PC1/SO0
PCD register "0" after a reset PCPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input VDIO PC register VDIO
Hi-Z
PCD register "0" after a reset VDIO
PC2/SI0 PC3/SCS0
Hi-Z
PCPUL register "0" after a reset Data bus RD SI0, SCS0 MPX Input data latch IP CMOS Schmitt input
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CXR704060
Pin
Circuit format
VDIO PD register
After a reset
PDD register "0" after a reset VDIO
PDPUL register
PD0/CONNECT PD1/XVDATA PD2/DPLS PD3/DMNS
"0" after a reset PDSL register "0" after a reset
Hi-Z
Data bus RD
MPX Input data latch IP CMOS Schmitt input
To USB interface CONNECT, XVDATA, DPLS, DMNS
MPX CONNECT, XVDATA, DPLS, DMNS Signals from internal USB transceiver
TXDPLS, TXDMNS, TXENL, SUSPEND MPX PD register PDSL register "0" after a reset
VDIO
PD4/TXDPLS PD5/TXDMNS PD6/TXENL PD7/SUSPEND
PDD register "0" after a reset PDPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input VDIO
Hi-Z
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CXR704060
Pin
TXD0, TXD1
Circuit format
VDIO MPX PE register PESL register "0" after a reset PED register
After a reset
PE0/TXD0 PE2/TXD1
"0" after a reset PEPUL register "0" after a reset Data bus RD MPX Input data latch
VDIO
Hi-Z
IP CMOS Schmitt input
VDIO PE register
PED register
PE1/RXD0 PE3/RXD1 PE6/SI1 PE7/SCS1
"0" after a reset
VDIO
Hi-Z
PEPUL register "0" after a reset Data bus RD RXD0, RXD1, SI1, SCS1 MPX Input data latch IP CMOS Schmitt input
VDIO SCK1 MPX PE register PESL register "0" after a reset SCK1E MPX PED register
PE4/SCK1
"0" after a reset PEPUL register "0" after a reset Data bus RD SCK1 MPX Input data latch
VDIO
Hi-Z
IP CMOS Schmitt input
- 16 -
CXR704060
Pin
Circuit format
VDIO SO1 MPX PE register PESL register "0" after a reset SO1E MPX
After a reset
PE5/SO1
PED register "0" after a reset PEPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input VDIO
Hi-Z
VDIO PF register
PFD register "0" after a reset VDIO
PF0/EC0/INT3 PF2/EC2/INT4
PFPUL register "0" after a reset Data bus RD EC0,EC2 INT3, INT4 MPX Input data latch IP CMOS Schmitt input
Hi-Z
T1, T3 MPX PF register PFSL register "0" after a reset PFD register
VDIO
PF1/T1 PF3/T3
"0" after a reset PFPUL register "0" after a reset Data bus RD MPX Input data latch
VDIO
Hi-Z
IP CMOS Schmitt input
- 17 -
CXR704060
Pin
Circuit format
VDIO BEEP PF register "0" after a reset MPX
After a reset
PF4/BEEP
PFSL register BEEPE Data bus RD
Hi-Z
DACK0 MPX PG register PGSL register "0" after a reset PGD register
VDIO
PG0/DACK0
"0" after a reset PGPUL register "0" after a reset Data bus RD MPX Input data latch
VDIO
Hi-Z
IP CMOS Schmitt input
VDIO PG register
PGD register "0" after a reset
PG1/DREQ0/ INT5 PG3/DREQ1/ INT7
VDIO PGPUL register "0" after a reset Data bus RD DREQ0, DREQ1 INT5, INT7 MPX Input data latch IP CMOS Schmitt input
Hi-Z
- 18 -
CXR704060
Pin
DACK1
Circuit format
VDIO MPX PG register PGSL register "0" after a reset PGD register
After a reset
PG2/DACK1/ INT6
"0" after a reset PGPUL register "0" after a reset Data bus RD INT6 MPX Input data latch
VDIO
Hi-Z
IP CMOS Schmitt input
DADT, FS256, MUTFGL, MUTFGR MPX PI register PISL register "0" after a reset
VDIO
PI0/DADT PI4/FS256 PI5/MUTFGL PI6/MUTFGR
PID register "0" after a reset PIPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input
VDIO PI register
VDIO
Hi-Z
PID register "0" after a reset VDIO
PI1/ADDT
PIPUL register "0" after a reset Data bus RD ADDT MPX Input data latch IP CMOS Schmitt input
Hi-Z
- 19 -
CXR704060
Pin
Circuit format
VDIO LRCK, XBCK MPX PI register PISL register "0" after a reset LRCKE, XBCKE MPX
After a reset
PI2/LRCK PI3/XBCK
PID register "0" after a reset PIPUL register "0" after a reset Data bus RD LRCK, XBCK MPX Input data latch IP CMOS Schmitt input VDIO
Hi-Z
VDIOMS PI register
PID register "0" after a reset VDIOMS
PI7
PIPUL register "0" after a reset Data bus RD MPX Input data latch CMOS Schmitt input IP
Hi-Z
VDIO PJ register
PJD register "0" after a reset VDIO
PJ0/WAIT
PJPUL register "0" after a reset Data bus RD WAIT MPX Input data latch IP CMOS Schmitt input
Hi-Z
- 20 -
CXR704060
Pin
RE, LWR/LB, UWR/UB, WE
Circuit format
VDIO MPX PJ register PJSL register "0" after a reset
After a reset
PJ1/RE PJ2/LWR/LB PJ3/UWR/UB PJ4/WE
PJD register "0" after a reset PJPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input VDIO
Hi-Z
CS0, CS1, CS5 to CS7 MPX PK register PKSL register
VDIO
PK0/CS0 to PK1/CS1 PK5/CS5 to PK7/CS7
"0" after a reset PKD register "0" after a reset PKPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input VDIO
Hi-Z
VDIO PK register
PKD register "0" after a reset VDIO
PK2 to PK4
PKPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input
Hi-Z
- 21 -
CXR704060
Pin
Circuit format
VDIO A0 to A7 MPX PL register PLSL register "0" after a reset AE
After a reset
PL0/A0 to PL7/A7
MPX PLD register "0" after a reset PLPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input VDIO
Hi-Z
VDIO A8 to A15 MPX PM register PMSL register "0" after a reset AE
PM0/A8 to PM7/A15
MPX PMD register "0" after a reset PMPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input VDIO
Hi-Z
- 22 -
CXR704060
Pin
Circuit format
VDIO A16 to A23 MPX PN register PNSL register "0" after a reset AE
After a reset
PN0/A16 to PN7/A23
MPX PND register "0" after a reset PNPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input VDIO
Hi-Z
VDIO D0 to D7 MPX PO register POSL register "0" after a reset DE
PO0/D0 to PO7/D7
MPX POD register "0" after a reset POPUL register "0" after a reset Data bus RD D0 to D7 MPX Input data latch IP CMOS Schmitt input VDIO
Hi-Z
VDIO PP register
PPD register "0" after a reset VDIO
PP0 PP1
Hi-Z
PPPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input
- 23 -
CXR704060
Pin
Circuit format
VDIO PQ register
After a reset
PQD register "0" after a reset VDIO
PQ0 to PQ7
PQPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input
Hi-Z
VDIO PR register
PRD register "0" after a reset VDIO
PR0 to PR7
PRPUL register "0" after a reset Data bus RD MPX Input data latch IP CMOS Schmitt input
Hi-Z
RST
AN0 to AN5
To A/D converter AN0 to AN5
IP
Hi-Z
RST To A/D converter AN6, AN7 IP
AN6/INT8 AN7/INT9
Hi-Z
INT8, INT9 AVDAD x (0.7 0.1)
- 24 -
CXR704060
Pin
FAD0 to FAD7 output data FAD0 to FAD7 output enable
Circuit format
VDIODF
After a reset
FAD0 to FAD7
FAD0 to FAD7 pull-up control FAD0 to FAD7 input data CMOS Schmitt input
VDIODF
"L" output
IP
FCLE FALE FWE FRE, FWR, FCE0, FCE1
VDIODF
FCL, FALE, FWE, FRE, FWR, FCE0, FCE1
"L" output
FRB0, FRB1
FRB0 FRB1
CMOS Schmitt input
"L" output
IP
KDI KRB
IP
KDI, KRB
Hi-Z
VDIO
KDO
KDO
"L" output
VDIO
KCS KCLK
KCS, KCLK
"H" output
EVA
IP
EVA
Hi-Z
VBUS
IP
VBUS
Hi-Z
- 25 -
CXR704060
Pin
Circuit format
VDIOUS TRON output data
After a reset
TRON
TRON output enable
Hi-Z
VDIOMS MSDIO output data
MSDIO output enable
MSDIO
MSDIO input data CMOS Schmitt input IP
Hi-Z
VDIOMS
MSBS MSSCLK
MSBS, MSSCLK
"L" output
MSINS
IP
MSINS
Hi-Z
AVDMO
EXTAL XTAL
EXTAL
IP
* Diagram shows the circuit configuration during oscillation. * XTAL is "H" level when oscillation is stopped.
Oscillation
XTAL
AVDUO
TEX TX
TEX
IP
* Diagram shows the circuit configuration during oscillation. * TX is "H" level when oscillation is stopped.
Oscillation
TX
- 26 -
CXR704060
Pin RAMBK
Circuit format
IP RAMBK
After a reset Hi-Z
VDIOJT
TDI TMS TCK
IP TDI, TMS, TCK
Pull-up
IP
TRST
TRST
VDIOJT
Pull-down
VDIOJT TDO output data
TDO
TDO output enable
Hi-Z
IP
RST
RST (to reset circuit) To AN0 to AN7
Hi-Z
IP
TEST0
CMOS Schmitt input
TEST0 (to test circuit)
Hi-Z
TEST1 to TEST3
IP
TEST1 to TEST3 (to test circuit)
Hi-Z
IP
TEST4
VDIO
TEST4 (to test circuit) CMOS Schmitt input
Pull-down
VDIO
TEST5 TEST6
TEST5, TEST6 (from test circuit)
"L" output
- 27 -
CXR704060
Absolute Maximum Ratings Item Symbol DVDD VDBK AVDAD AVDDA AVDMO AVDUO Supply voltage AVDPLL VDIO VDIODF VDIOJT VDIOUS VDIOMS Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VIN VINR VOUT IOH IOH IOL IOL Topr Tstg PD Rating -0.3 to +2.5 -0.3 to +2.5 -0.3 to +4.5 -0.3 to +4.5 -0.3 to +4.5 -0.3 to +4.5 -0.3 to +4.5 -0.3 to +4.5 -0.3 to +4.5 -0.3 to +4.5 -0.3 to +4.5 -0.3 to +4.5 -0.3 to +4.51 -0.3 to +2.52 -0.3 to +4.51 -5 -40 10 80 -20 to +70 -55 to +150 380 Unit V V V V V V V V V V V V V V V mA mA mA mA C C mW
(DVSS = 0V reference) Remarks DVDD0, DVDD1, DVDD2, DVDD3 Power supply for backup RAM
VDIO0, VDIO1, VDIO2, VDIO3, VDIO4, VDIO5, VDIO6, VDIO7
Excludes RST and RAMBK pins RST and RAMBK pins Output (value per pin) Total for all output pins Output (value per pin) Total for all output pins
1 VIN and VOUT must not exceed I/O supply voltage (VDIO, VDIODF, VDIOJT, VDIOUS and VDIOMS) + 0.3V. 2 VINR must not exceed DVDD + 0.3V. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
- 28 -
CXR704060
Recommended Operating Conditions Item Internal supply voltage Supply voltage for internal RAM backup DAC supply voltage Main oscillation voltage Sub oscillation voltage PLL voltage I/O voltage JTAG voltage Symbol DVDD VDBK Min. 1.1 1.1 2.2 2.2 2.2 2.7 2.7 DVDD 1.65 2.7 2.7 3.0 0.7DVDD 0.7VDBK 0.7VDIO 0.7VDIOMS 0.7VDIODF 0.7VDIO 0.7VDIOJT 0.7VDIOMS 0.8AVDAD 0 0 0 0 0 0 0 0 0 -20 3.3 Typ. Max. 1.3 1.3 3.3 3.3 3.3 3.3 3.3 3.6 3.3 3.6 3.6 3.45 DVDD VDBK VDIO VDIOMS VDIODF VDIO VDIOJT VDIOMS AVDAD 0.2DVDD 0.2VDBK 0.2VDIO 0.2VDIOMS 0.2VDIODF 0.2VDIO 0.2VDIOJT 0.2VDIOMS 0.6AVDAD +70 Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V C RST pin 1
(DVSS = 0V reference) Remarks DVDD0, DVDD1, DVDD2, DVDD3
AD converter supply voltage AVDAD AVDDA AVDMO AVDUO AVDPLL VDIO VDIOJT
VDIO0, VDIO1, VDIO2, VDIO3, VDIO4, VDIO5, VDIO6, VDIO7
FLASH I/F voltage with ECC VDIODF Memory Stick I/F voltage VDIOMS USB transceiver voltage VDIOUS VIHR VIHBK VIHS VIHMSS High level input voltage VIHDFS VIHC VIHJTC VIHMSC VIHKW VILR VILBK VILS VILMSS Low level input voltage VILDFS VILC VILJTC VILMSC VILKW Operating temperature 1 2 3 4 5 6 7 8 Topr
RAMBK pin CMOS Schmitt trigger input2 CMOS Schmitt trigger input3 CMOS Schmitt trigger input4 CMOS input5 CMOS input6 CMOS input7 AN6 and AN7 pins8 RST pin RAMBK pin CMOS Schmitt trigger input2 CMOS Schmitt trigger input3 CMOS Schmitt trigger input4 CMOS input5 CMOS input6 CMOS input7 AN6 and AN7 pins8
VDBK should be the same voltage as DVDD (DVDD 0.1V or less). Each pin of normal input ports (PA to PE, PF0 to PF3, PG, PI0 to PI6, PJ to PR, TEST0). MSDIO and PI7 pins. FAD0 to FAD7, FRB0 and FRB1 pins. KDI, KRB, TEST1 to TEST4, EVA and VBUS pins. TDI, TMS, TCK and TRST pins. MSINS pins. Do not set AN6 and AN7 to the center potential in the steady state. (Low level input voltage: 0 to 0.4V, High level input voltage: (AVDAD - 0.4V) to AVDAD) - 29 -
CXR704060
Electrical Characteristics DC Characteristics (DVDD = VDBK = 1.1 to 1.3V, AVDAD = AVDDA = AVDMO = 2.2 to 3.3V, AVDUO = AVDPLL = 2.7 to 3.3V) (VDIO = VDIODF = VDIOMS = 2.7 to 3.6V, VDIOJT = 2.7 to 3.3V, VDIOUS = 3.0 to 3.45V) (Topr = -20 to +70C, DVSS = 0V reference) Item Symbol Pins PA0/PWM, PB, PD to PG, PI0 to PI6, PJ to PR 1 PI7 Conditions VDIO = 2.7V, IOH = -2.0mA VDIOMS = 2.7V, IOH = -2.0mA Min. VDIO - 0.4 VDIOMS - 0.4 Typ. Max. Unit V V
High level output voltage
VOH
D0 to D15, PC0/SCK0, PC1/SO0, PC2, PC3, TXDPLS, TXDMNS, TXENL, SUSPEND, TXD0, TXD1, SCK1, SO1, BEEP, DACK0, VDIO = 2.7V, DACK1, DADT, LRCK, IOH = -4.0mA XBCK, FS256, MUTFGL, MUTFGR, RE, LWR/LB, UWR/UB, WE, CS0, CS1, CS5 to CS7, A0 to A23, KDO, KCLK, KCS 2 TDO TRON MSDIO, MSBS, MSSCLK FAD0 to FAD7, FCLE, FALE, FWE, FRE, FWP, FCE0, FCE1 PA0/ PWM, PB, PD to PG, PI0 to PI6, PJ to PR 1 PI7 FRB0, FRB1 VDIOJT = 2.7V, IOH = -4.0mA VDIOUS = 3.0V, IOH = -4.0mA VDIOMS = 2.7V, IOH = -4.0mA VDIODF = 2.7V, IOH = -4.0mA VDIO = 2.7V, IOL = 2.0mA VDIOMS = 2.7V, IOL = 2.0mA VDIODF = 2.7V, IOL = 2.0mA
VDIO - 0.4
V
VDIOJT - 0.4 VDIOUS - 0.4 VDIOMS - 0.4 VDIODF - 0.4 0.4 0.4 0.4
V V V V V V V
Low level output voltage
VOL
PA1/ SDA, PA2/SCL, D0 to D15, PC0/SCK0, PC1/SO0, PC2, PC3, TXDPLS, TXDMNS, TXENL, SUSPEND, TXD0, TXD1, SCK1, SO1, BEEP, DACK0, VDIO = 2.7V, DACK1, DADT, LRCK, IOL = 4.0mA XBCK, FS256, MUTFGL, MUTFGR, RE, LWR/LB, UWR/UB, WE, CS0, CS1, CS5 to CS7, A0 to A23, KDO, KCLK, KCS 2 TDO VDIOJT = 2.7V, IOL = 4.0mA - 30 -
0.4
V
0.4
V
CXR704060
Item
Symbol TRON
Pins
Conditions VDIOUS = 3.0V, IOL = 4.0mA VDIOMS = 2.7V, IOL = 4.0mA VDIODF = 2.7V, IOL = 4.0mA VDIO = 2.7V, VIL = VSS VDIO = 3.6V, VIL = VSS VDIOMS = 2.7V, VIL = VSS VDIOMS = 3.6V, VIL = VSS VDIODF = 2.7V, VIL = VSS VDIODF = 3.6V, VIL = VSS VDIO = 3.6V, VI = 3.6V VDIOJT = 3.3V, VI = 3.3V VDIOUS = 3.45V, VI = 3.45V VDIOMS = 3.6V, VI = 3.6V VDIODF = 3.6V, VI = 3.6V AVDAD = 3.3V, VI = 3.3V VDBK = 1.3V, VI = 1.3V VDIO = 3.6V, VI = 0V VDIOJT = 3.3V, VI = 0V VDIOUS = 3.45V, VI = 0V VDIOMS = 3.6V, VI = 0V - 31 -
Min.
Typ.
Max. 0.4 0.4 0.4
Unit V V V A
Low level output voltage
VOL
MSDIO, MSBS, MSSCLK FAD0 to FAD7, FCLE, FALE, FWE, FRE, FWP, FCE0, FCE1 PA to PG, PI0 to PI6, PJ to PR
-30 -150 -30 -150 -30 -150
A A A A A
Input current
IIL3
PI7
FAD0 to FAD7
PA to PG, PI0 to PI6, PJ to PR, KDI, KRB, KDO, KCLK, KCS, TEST0 to TEST6, EVA, VBUS TDO TRON IZH 3 PI7, MSDIO, MSBS, MSSCLK, MSINS FAD0 to FAD7, FCLE, FALE, FWE, FRE, FWP, FCE0, FCE1, FRB0, FRB1 AN0 to AN7 RAMBK, RST PA to PG, PI0 to PI6, PJ to PR, KDI, KRB, KDO, KCLK, KCS, TEST0 to TEST6, EVA, VBUS IZL TDO TRON PI7, MSDIO, MSBS, MSSCLK, MSINS
10
A
10 10 10 10 10 10
A A A A A A
I/O leakage current
-10
A
-10 -10 -10
A A A
CXR704060
Item
Symbol
Pins FAD0 to FAD7, FCLE, FALE, FWE, FRE, FWP, FCE0, FCE1, FRB0, FRB1
Conditions VDIODF = 3.6V, VI = 0V AVDAD = 3.3V, VI = 0V VDBK = 1.3V, VI = 0V Clock 1MHz 0V except the measured pins
Min.
Typ.
Max. -10 -10 -10
Unit A A A
I/O leakage current
IZL
AN0 to AN7 RAMBK, RST PA to PG, PI to PR, AN0 to AN7, FAD0 to FAD7, FRB0, FRB1, MSDIO, MSINS, KRB, KDI, EVA, TEST0 to TEST4, RAMBK, RST
Input CIN capacitance
11
pF
1 When used as PA0/PWM, PB, PD to PG and PI to PO, specified at IOH = -2.0mA and IOL = 2.0mA. 2 When used as PA1/SDA, PA2/SCL, PC and dual function pins, specified at IOH = -4.0mA and IOL = 4.0mA. 3 The PA to PG, PI to PR and FAD0 to FAD7 pins specify the input current when the pull-up resistor is selected, and specify the leakage current when non-resistor is selected.
(Topr = -20 to +70C, DVDD = 1.1 to 1.3V, DVss = 0V reference) Item Pins Symbol IDD1 Conditions Main execution mode2 fSRC = 22.58MHz crystal oscillation 1/2 frequency division (11.29MHz) (C1 = C2 = 10pF)4 Main execution mode3 fSRC = 22.58MHz crystal oscillation (C1 = C2 = 10pF)4 Main idle mode fSRC = 22.58MHz crystal oscillation (C1 = C2 = 10pF)4 Stop mode Ta = 25C (DVDD = 1.2V) Ta = -20 to +50C Min. -- Typ. 4.5 Max. 7.5 Unit mA
Supply current1
IDD2 DVDD/VDBK IDDI IDDS1 IDDS2
--
--
29
mA
--
3.5 100 --
6.5 300 1500
mA
--
A
1 2 3 4
When all output pins are left open, this indicates the current flowing to DVDD and VDBK. During ATRAC3 decoding operation. When the arithmetic accelerator circuit is always operating. C1 and C2 indicate the external capacitors attached to the EXTAL and XTAL pins, respectively.
- 32 -
CXR704060
AC Characteristics (1) EXTAL pins 1) Automatic oscillation (Topr = -20 to +70C, DVDD = VDBK = 1.1 to 1.3V, AVDMO = 2.2 to 3.3V, AVSOSC = DVss = 0V reference) Item Oscillation frequency Symbol fSRC Conditions Min. 22.4 Typ. 22.5792 Max. 22.8 Unit MHz
2) When inputting pulses to EXTAL pin (Topr = -20 to +70C, DVDD = VDBK = 1.1 to 1.3V, AVDMO = 2.2 to 3.3V, AVSOSC = DVss = 0V reference) Item High level pulse width Low level pulse width Pulse period Input high level Input low level Rise time, fall time Symbol tWHX tWLX tCX VIHX VILX tR, tF Conditions Min. 16 16 43.9 0.7AVDMO 0.2AVDMO 7 44.6 Typ. Max. Unit ns ns ns V V ns
Note) When the clock is supplied externally, input to the EXTAL pin and input an opposite phase clock to the XTAL pin.
tCX tWHX tWLX VIHX VIHX - (VIHX - VILX) x 0.1
EXTAL
AVDMO/2
tR
tF
VILX + (VIHX - VILX) x 0.1 VILX
Fig. 1. Main Clock Timing
- 33 -
CXR704060
(2) TEX pin 1) Automatic oscillation (Topr = -20 to +70C, DVDD = VDBK = 1.1 to 1.3V, AVDUO = 2.7 to 3.3V, AVSOSC = DVss = 0V reference) Item Oscillation frequency Symbol fTEX Conditions Min. 8 Typ. Max. 16 Unit MHz
2) When inputting pulses to TEX pin (Topr = -20 to +70C, DVDD = VDBK = 1.1 to 1.3V, AVDUO = 2.7 to 3.3V, AVSOSC = DVss = 0V reference) Item High level pulse width Low level pulse width Pulse period Input high level Input low level Rise time, fall time Symbol tWHTX tWLTX tCTX VIHTX VILTX tR, tF Conditions Min. 25 25 62.5 0.7AVDUO 0.2AVDUO 7 125 Typ. Max. Unit ns ns ns V V ns
Note) When the clock is supplied externally, input to the TEX pin and input an opposite phase clock to the TX pin.
tCTX tWHTX tWLTX VIHTX VIHTX - (VIHTX - VILTX) x 0.1
TEX
AVDUO/2
tR
tF
VILTX + (VIHTX - VILTX) x 0.1 VILTX
Fig. 2. Sub Clock Timing
- 34 -
CXR704060
3) Serial transfer (CH0, CH1) (Topr = -20 to +70C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference) Item SCK cycle time SCK high, low pulse width SI input setup time (for SCK) SI input hold time (for SCK) SCK SO delay time Note Note Note Note Symbol tKCY tKH tKL tSIK tKSI tKSO Pins SCK0 SCK1 SCK0 SCK1 SI0 SI1 SI0 SI1 SO0 SO1 Conditions Input mode Output mode Input mode Output mode SCLK input mode SCLK output mode SCLK input mode SCLK output mode SCLK input mode SCLK output mode Min. 6/fPS2 1/fSCK 3/fPS2 0.5/fSCK - 5 -2/fPS2 + 5 35 2/fPS2 + 5 0 -- -- Max. -- -- -- -- -- -- -- -- 3/fPS2 + 40 5 Unit ns ns ns ns ns ns ns ns ns ns
1) The load capacitance of the measurement pin is 75pF. 2) fSCK: Serial clock 3) fPS2: PS2 clock (fPS2 = fSRC/4) 4) fSCK = fPS2/{2 x (Register setting value + 1)}: Register setting value (01h to FFh)
tKCY tKL tKH
SCK0 SCK1
tSIK
tKSI
SI0 SI1
Input data
tKSO
SO0 SO1
Output data
Fig. 3. Serial CH0 and CH1 Transfer Timing
- 35 -
CXR704060
4) Serial transfer (Memory Stick) (Topr = -20 to +70C, DVDD = 1.1 to 1.3V, VDIOMS = 2.7 to 3.6V, DVSS = 0V reference) Item MSSCLK cycle time MSSCLK high, low pulse width MSBS output delay time MSDIO output delay time MSDIO input setup time MSDIO input hold time Symbol tKCY tBSD tDIOD tDIOS tDIOH Pins MSSCLK MSBS MSDIO MSDIO MSDIO For MSSCLK For MSSCLK For MSSCLK For MSSCLK Conditions Min. 1000/fMSCK 500/fMSCK - 5 -- -- 14 5 Max. -- -- 10 10 -- -- Unit ns ns ns ns ns ns
tKH, tKL MSSCLK
Note 1) The load capacitance is 26pF. Note 2) The oscillation of the TEX pin is at 50% duty. Note 3) fMSCK is as follows for fSRC from the main oscillation circuit or fTEX from the sub oscillation circuit.
Shift clock frequency division ratio Main oscillation 1/2 frequency division Main oscillation 1/4 frequency division Sub oscillation
fMSCK [MHz] fSRC/2 fSRC/4 fTEX
tKCY 0.7VDIOMS MSSCLK 0.2VDIOMS tKL tKH
MSBS tBSD
Bus state output
MSDIO (output)
Output data tDIOD
MSDIO (input)
Input data tDIOS tDIOH
Fig. 4. Memory Stick Transfer Timing
- 36 -
CXR704060
5) Flash memory interface characteristics (Topr = -20 to +70C, DVDD = 1.1 to 1.3V, VDIODF = 2.7 to 3.3V, DVSS = 0V reference) Item FRE low pulse width FRE setup time FRE hold time FEW low pulse width FWE setup time FWE hold time Symbol tRECY tRSFA tRHFA tWECY tWSFA tWHFA Pins FRE FAD[7:0] FAD[7:0] FWE FAD[7:0] FAD[7:0] Conditions Min. T x (RSTB setting value) - 10 35 0 T x (WSTB setting value) - 10 T x (WSTP setting value + WSTB setting value) - 10 T x (WHLD setting value) - 10 Max. -- -- -- -- -- -- Unit ns ns ns ns ns ns
Note 1) "T" indicates the 1 cycle (1/fSRC) of the system clock. Note 2) RSTB, WSTB, WSTP and WHLD indicate the register set to the flash memory interface WE/RE timing register (FIWERETR). See the table below for allowable setting values. Note 3) The load capacitance of the measurement pin is 75pF.
RSTB, WSTB, WSTP and WHLD setting value Item WSTP WSTB WHLD RSTB Bits within FIWERETR register [27:24] [23:20] [19:16] [7:4] Allowable setting values 0h to Fh 0h to Fh 0h to Fh 0h to Fh
- 37 -
CXR704060
* During Read
tRECY
FRE
VDIODF/2
tRSFA
tRHFA
FAD[7:0]
* During Write
tWECY
FWE
VDIODF/2
tWSFA
tWHFA
FAD[7:0]
Fig. 5. Flash Memory Interface Transfer Timing with ECC
- 38 -
CXR704060
6) Bus interface unit (BIU) characteristics * 2-cycle access AC characteristics parameter in write operation (Topr = -20 to +70C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference) Item Address setup time for UWR (UB) and LWR (LB) CS and WE setup time for UWR (UB) and LWR (LB) Address hold time for UWR (UB) and LWR (LB) CS and WE hold time for UWR (UB) and LWR (LB) UWR (UB) and LWR (LB) low pulse width Data setup time for UWR (UB) and LWR (LB) Data hold time for CS and WE Note) The load capacitance of the measurement pin is 75pF. Symbol tADULD1 tCWULD1 tULADD1 tULCWD1 tWUL1 tDULD1 tDD1 Min. 3/2fSRC - 5 3/2fSRC - 5 1/2fSRC - 5 1/2fSRC - 5 1/fSRC 1/2fSRC - 5 0 Max. -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
Tw
T1
T2
Address tADULD1 CS, WE tCWULD1 UWR, UB, LWR, LB tWUL1 tULCWD1 tULADD1
RD
tDULD1 Valid
tDD1
D15 to D0
Fig. 6. 2-cycle Access Basic Timing in Write Operation
- 39 -
CXR704060
* 3-cycle access AC characteristics parameter in write operation (Topr = -20 to +70C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference) Item Address setup time for UWR (UB) and LWR (LB) CS and WE setup time for UWR (UB) and LWR (LB) Address hold time for UWR (UB) and LWR (LB) CS and WE hold delay time for UWR (UB) and LWR (LB) UWR (UB) and LWR (LB) low pulse width Data setup time for UWR (UB) and LWR (LB) Data hold time for CS and WE Note) The load capacitance of the measurement pin is 75pF. Symbol tADULD2 tCWULD2 tULADD2 tULCWD2 tWUL2 tDULD2 tDD2 Min. 2/fSRC - 5 2/fSRC - 5 1/fSRC - 5 1/fSRC - 5 1/fSRC 1/fSRC - 5 0 Max. -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
Tw
T1
T2
T3
Address tADULD2 CS, WE tCWULD2 UWR, UB, LWR, LB tWUL2 tULCWD2 tULADD2
RD
tDULD2 Valid
tDD2
D15 to D0
Fig. 7. 3-cycle Access Basic Timing in Write Operation
- 40 -
CXR704060
* 2-cycle access AC characteristics parameter in read operation (Topr = -20 to +70C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference) Item Address, CS and WE setup time for UWR (UB) and LWR (LB) UWR (UB) and LWR (LB) low pulse width Address, CS and WE hold time for UWR (UB), LWR (LB) and RD Data setup time for UWR (UB), LWR (LB) and RD Data hold time for UWR (UB), LWR (LB) and RD Note) The load capacitance of the measurement pin is 75pF.
T1 T2
Symbol tADULD3 tWUL3 tULADD3 tRDS1 tRDH1
Min. 1/2fSRC - 5 1/fSRC 1/2fSRC - 5 1/2fSRC + 23 0
Max. -- -- -- -- --
Unit ns ns ns ns ns
Address CS, WE tADULD3 UWR, UB, LWR, LB, RD tWUL3 tULADD3
tRDS1 D15 to D0 Valid data in
tRDH1
Fig. 8. 2-cycle Access Basic Timing in Read Operation
- 41 -
CXR704060
* 3-cycle access AC characteristics parameter in read operation (Topr = -20 to +70C, DVDD = 1.1 to 1.3V, VDIO = 2.7 to 3.3V, DVSS = 0V reference) Item Address, CS and WE setup time for UWR (UB), LWR (LB) and RD UWR (UB) and LWR (LB) low pulse width Address, CS and WE hold time for UWR (UB), LWR (LB) and RD Data setup time for UWR (UB), LWR (LB) and RD Data hold time for UWR (UB), LWR (LB) and RD Note) The load capacitance of the measurement pin is 75pF. Symbol Min. Max. -- -- -- -- -- Unit ns ns ns ns ns
tADULD4 1/fSRC - 5 tWUL4 tRDS2 tRDH2 1/fSRC 24 0 tULADD4 1/fSRC - 5
T1
T2
T3
Address CS, WE tADULD4 UWR, UB, LWR, LB, RD tWUL4 tULADD4
tRDS2 D15 to D0
tRDH2
Valid data in
Fig. 9. 3-cycle Access Basic Timing in Read Operation
- 42 -
CXR704060
7) A/D converter characteristics (Topr = -20 to +70C, DVDD = 1.1 to 1.3V, AVDAD = 2.2 to 3.0V, DVss = 0V, AVSAD = 0V reference) Item Resolution Absolute error Differential linearity error Integral linearity error Conversion time Sampling time Analog input voltage tCONV tSAMP VIAN Symbol Pins -- -- -- -- -- -- AN0 to AN7 Min. -- -- -- -- 19/fPS4 -- 0 Typ. -- -- -- -- -- 3/fPS4 -- Max. 10 7 1 3 20/fPS4 -- AVDAD Unit Bits LSB LSB LSB s s V
Note) fPS4 is fSRC/16 [MHz] relative to the main oscillation circuit output fSRC. Conversion time indicates the time required from the start of conversion when one channel is selected until the ADC interrupt request is generated, and also includes the sampling time.
Differential linearity error (Code center interval offset) A/D conversion line
3FFh 3FEh
Digital conversion value
Digital conversion value
Absolute error
A/D conversion results
Integral linearity error (Code center offset from AD conversion line) 001h 000h AVDAD Analog input voltage Analog input voltage
Fig. 10. Definition of A/D Converter Terms
- 43 -
CXR704060
Internal DAC Specifications 1) Digital filter characteristics Pass band Stop band Pass band ripple Stop band attenuation 0 [Hz] to 20 [kHz] 24.1 to 328.7 [kHz] 0.03 [dB] or less 54 [dB] or more
2) Analog characteristics Item S/N THD + N Dynamic range Gain difference between channels Output voltage1 Output load resistor Analog filter cutoff frequency Min. -- -- -- -- -- 10 --
(AVDDA = 2.4V, Ta = 25C) Typ. 92 0.015 93 0.1 666.2 -- 90 Max. -- -- -- 0.15 -- -- -- Unit dB % dB dB or less Vrms k or more kHz
1 The output voltage is approximately 0.8AVDDA [Vp-p].
- 44 -
CXR704060
Package Outline
Unit: mm
208PIN TFLGA
0.20 S A 13.0
X
PIN 1 INDEX
1.1MAX
13.0
0.1 MAX
x4
0.15
3-
1.0
(0.55)
(0.55)
1.075 0.65
0.20 S B
0.20 S
A 208- 0.35 0.05 0.08 M S AB
DETAIL X
V
U
1.075
T R P
0.325
N M L K J H G F
B
0.65
1.075 1.0
E D C B A
(0.55)
1.0 1.075
0.325
0.975
678 4 012 1 2 3 4 5 6 7 8 9 1 1 1 13 1 15 1 1 1
C0.3 (0.55)
0.975
PACKAGE STRUCTURE
PACKAGE MATERIAL ORGANIC SUBSTRATE TERMINAL TREATMENT NICKEL & GOLD PLATING TERMINAL MATERIAL PACKAGE MASS COPPER 0.39g
SONY CODE EIAJ CODE JEDEC CODE
TFLGA-208P-01 P-TFLGA-208-13.0x13.0-0.65
- 45 -
Sony Corporation
0.10 S

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